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STC12C5A60S2 is a single-chip microcontroller based on a high performance 1T architecture 80C51 CPU, which is produced by STC MCU Limited. With the enhanced kernel, STC12C5A60S2 executes instructions in 1~6 clock cycle (about 6~7 times the rate of a standard 8051 device), and has a fully compatible instruction set with industrial-standard 80C51 series microcontroller. In-System-Programming(ISP) and In-Application-Programming(IAP) support the users to upgrade the program and data in sytem.
| Enhanced 80C51 Central Processing Unit, 1T per machine cycle, faster 6~7 times than the rate of a standard 8051. | |
| 60K Bytes of In-System Programmable (ISP) Flash Memory | |
| 1280 x 8-bit Internal RAM | |
| Four 16-bit Timer/Counters | |
| 10 vector-address, 4 level priority interrupt capability | |
| One enhanced UART with hardware address-recognition and frame-error detection function | |
| Secondary UART with self baud-rate generator | |
| Two channel Programmable Counter Array(PCA) | |
| 10-bit, 8-channel Analog-to-Digital Converter(ADC) | |
| Three power management modes : idle mode, slow down mode and power-down mode | |
| Interrupt Recovery from Power-down Mode | |
| Watchdog Timer | |
| Dual Data Pointer | |
| 36 Programmable I/O Lines | |
| 40-lead PDIP | |
| Operating Voltage : 3.5V - 5.5V | |
| 0 - 35MHz |
| 1 Ref. Doc. | Download |
